1. Field of Application
The present invention relates to a compiler for generating object code to be executed by a RISC (Reduced Instruction Set Computer) type of CPU (Central Processing Unit), from source code of a computer program, and to a microcomputer having the object code stored in a program memory.
2. Description of Prior Art
Development of a program to be executed by a computer is generally performed by first writing the program as source code, in a high-level programing language such as C or C++. The source code is then compiled, i.e., converted by execution of a program referred to as a compiler, into object code consisting of successive instructions in machine language, which can be directly executed by the CPU of a computer. After the program source code has been compiled, the object code of the program is stored in memory at the computer which will utilize it, and the program can then be executed.
A RISC type of CPU is configured for execution of instructions from among a small set of object code instructions, which perform respective simple functions and can have short execution times. Each stage of a program, such as performing a “fetch”, “decode”, “write” operation, etc., is performed by executing a relatively large number of the RISC instructions, with these being executed in parallel as far as possible (i.e., using pipeline operation) in order to maximize the program execution speed. However the amount of such RISC object code that is generated from the source code of a program by the compiler is substantially greater than that which would be generated for the same program in the case of a CISC (Complex Instruction Set Computer) type of CPU.
FIG. 7 shows an instruction list that is an example of object code that might be generated by a prior art type of compiler for execution by a RISC type of CPU, for the following portion of source code:bit1 =bit2 & bit3  (1)
Here, bit1, bit2 and bit3 are names of respective bit variables, and the expression performs the AND logic function to obtain the logic product of the values of bit2 and bit3, and assigns the value of the result to the bit variable named bit1. An expression such as (1) above, which performs an operation on bit variables to obtain a result value which is assigned to a specified bit variable, will be referred to in the following and in the appended claims as a bit operational expression. It will be assumed that each of bit1, bit2 and bit3 is the fourth bit within a corresponding 8-bit variable (i.e., counting from the LSB of the 8-bit variable as the first bit). The 8-bit variables respectively containing bit1, bit2 and bit3 will be designated BIT1, BIT2 and BIT3 respectively.
FIG. 8 is a simple flow diagram showing the processing which would be executed by a prior art compiler to convert the source code of the above bit operational expression into object code. A1, A2, A3, and A4 designate successively generated portions of the object code.
In FIG. 7, the portion C1 of the object code effects an operation whereby the contents of the 8-bit variable BIT2 (which are held in memory) are read into a general-purpose register named reg1, then the contents of that register are right-shifted by three bit positions so that the desired fourth bit of the 8-bit variable is set in the LSB position in register reg1. The logic product of the contents of register reg1 and a set of mask data #$0001 (where the $ symbol indicates a base-16 number) is then derived, to thereby clear all of the bit positions in register reg1 other than the LSB position. The above portion C1 in FIG. 7 corresponds to step A1 in FIG. 8.
Portion C2 of the object code in FIG. 7 effects the same processing as that described above for the portion C1, but applied to the bit variable bit3 and utilizing a second general-purpose register, named reg2. This corresponds to step A2 in FIG. 8.
Portion C3 of the object code in FIG. 7 constitutes processing whereby the logic product of the respective contents of registers reg1 and reg2 is obtained. This corresponds to step A3 in FIG. 8. Next, in portion C4, the result of the logic product operation (which remains in register reg1) is left-shifted by three bit positions, then the contents of the 8-bit variable BIT1 are read into register reg2, and the logic product of the contents of register reg2 and the set of mask data bits #$fff7 is obtained, to thereby clear the bit which is at the fourth bit position in register reg2 while leaving the other contents of that register unchanged. The logic sum of the contents of the registers reg1, reg2 is then obtained, with the result of that operation being left in register reg2. The contents of register reg2 are then written into memory, to replace the previous contents of the 8-bit variable BIT1. This corresponds to step A4 in FIG. 8. This completes the processing sequence shown.
With a RISC type of CPU, since the instruction set is small, there are no dedicated instructions for reading out the values of bit variables. Hence it is necessary to use a plurality of other instructions, in combination, to perform such a function. As a result, in order to execute a bit operation which is written in source code as a single program step, it is necessary to use a total of 18 steps in the object code that is to be executed by a RISC CPU, with the example of FIG. 8. Hence, the memory capacity required to store a program that is to be executed by a RISC type of CPU becomes large, while in addition, the greater the number of steps that must be processed, the lower will become the program execution speed.
In the following, an expression representing processing whereby the value of a specified bit variable is judged or the respective values of a plurality of specified bit variables are judged, to obtain a binary (i.e., “true” or “false”) result and whereby specified operations are performed based on the judgement result, will be referred to as a condition judgement expression.